1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits and semiconductor devices, and, more particularly, to the formation of a transistor device having embedded stress-inducing layers in the source and drain regions adjacent to the channel region.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of N-channel transistors and P-channel transistors are formed on a substrate including a crystalline semiconductor layer.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the overall conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For example, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity in combination with a desired channel controllability. Moreover, the gate dielectric material may also be adapted to the reduced channel length in order to maintain the required channel controllability. However, some mechanisms for obtaining a high channel controllability may also have a negative influence on the charge carrier mobility in the channel region of the transistor, thereby partially offsetting the advantages gained by the reduction of the channel length.
Since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques and may also contribute to less pronounced performance gain due to mobility degradation, it has been proposed to enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to a future technology node while avoiding or at least postponing many of the process adaptations associated with device scaling.
One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region for a standard crystallographic configuration of the active silicon material, i.e., a (100) surface orientation with the channel length aligned to the <110> direction, increases the mobility of electrons, which, in turn, may directly translate into a corresponding increase in the conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors.
Particularly, it has been proposed to introduce a silicon/germanium layer next to the channel region to induce a compressive stress that may result in a corresponding strain. The strained silicon/germanium compound, which may also be referred to as a silicon/germanium alloy, may be provided in a strained state due to a mismatch of the lattice spacing between natural silicon and natural silicon/germanium alloy. That is, the silicon/germanium material may be formed on the basis of the silicon lattice spacing, thereby resulting in a strained silicon/germanium crystal lattice, which may then interact with the neighboring semiconductor material to exert a stress and thus cause a certain strain. The transistor performance of P-channel transistors may be considerably enhanced by the introduction of stress-creating layers next to the channel region. For this purpose, a strained silicon/germanium layer may be formed in the drain and source regions of the transistors, wherein the compressively strained drain and source regions create uniaxial strain in the adjacent silicon channel region. When forming the silicon/germanium layer, the drain and source regions of the PMOS transistors are selectively recessed, while the NMOS transistors are masked and subsequently the silicon/germanium layer is selectively formed in the PMOS transistor by epitaxial growth.
However, a particular problem arises when using the embedded silicon/germanium technique in the context of CMOS manufacturing and silicidated source/drain regions, as illustrated in FIGS. 1a and 1b. The conductivity of doped silicon-based semiconductor regions may be increased by providing a metal silicide therein in order to reduce overall sheet resistance and contact resistivity. For example, the drain and source regions may receive a metal silicide, such as nickel silicide, nickel platinum silicide and the like, thereby reducing the overall series resistance of the conductive path between the drain and source terminals and the intermediate channel region.
FIG. 1a shows a P-channel transistor 1 and an N-channel transistor 2 with channel regions 3 and 4 formed in a silicon layer 5. Each of the transistors 1 and 2 comprises a gate dielectric 6, 7, a gate layer 8, 9 and a silicidated top layer 10, 11, as well as sidewall spacers 12, 13. Moreover, each of the transistors 1 and 2 comprises a silicidated source (drain) region 14, 15 and a silicidated drain (source) region 14′, 15′. The P-channel transistor 2 comprises embedded silicon/germanium regions 16, 16′ as described above. They are doped in order to function as source/drain electrodes of the P-channel transistor 2. The transistor devices 1 and 2 are separated from each other by a shallow trench isolation (STI) 17 and covered by an interlayer dielectric 19.
As shown in FIG. 1a, the silicon/germanium material does not properly grow at the STI edge. Consequently, some “ski-sloped” area arises at the silicon-STI interface in the silicon layer 5. Since the silicon/germanium material does not properly grow at the STI edge, silicidation cannot properly be carried out. The silicon material of the silicon/germanium compound 16′ formed in the vicinity of the STI 17 (on the “ski-slope”) is too thin to allow for growing of the silicide material to an appropriate thickness. In a later manufacturing state, contact openings 18, 18′ are formed in the interlayer dielectric 19 for contacting the source/drain regions, as shown in FIG. 1b. 
Since the silicide material 15′ is not grown thickly enough, problems with contact landing arise. Particularly, the contact opening etch may not reliably stop on the silicide and etching deeply into the silicon/germanium compound 16′ may occur. Unconnected contacts that are formed in the contact opening 18′ formed above the sloped silicidated silicon/germanium compound 16′ may, therefore, cause device failures.
In view of the situation described above, the present disclosure provides techniques that allow for the formation of silicidated embedded semiconductor material adjacent to the channel region of a transistor within the CMOS manufacturing process that allow for a uniform growth of an embedded semiconductor material (for example, a silicon/germanium compound) even in the vicinity of an STI.